J Baskar

 J.Bhasker (he is called by his last name "Bhasker" and as "Bond" by his more intimate friends) has been involved with VHDL, Verilog HDL, and synthesis for more than ten years and he is one of the main architects of the ArchSyn synthesis system. He has coached a number of colleagues at AT&T/Lucent through classes on VHDL, Verilog HDL and synthesis.